1. Technical Field
The present invention generally relates to integrated circuits and in particular to leakage current in integrated circuits. Still more particularly, the present invention relates to compensation of leakage current in integrated circuits.
2. Description of the Related Art
Continued development in integrated circuit (IC) technology is driven by a desire for the ever decreasing size of circuit components on the IC die. As the technology scales down to deep sub-micron levels, the inter-die leakage variation increases dramatically. Large variations in device threshold voltage exist among dies, which lead to a wide range of die-to-die leakage spread across process corners.
The traditional design for worst-corner process variation using a fixed-strength keeper often over-compensates the leakage in the majority of dies of the low leakage corner in order to satisfy a small number of dies of the high leakage corner. Unfortunately, the high leakage dies still do not satisfy the robustness requirements with a keeper sized for the faster corner leakage. This over-compensation degrades the overall performance of the chip. The inability to satisfy performance requirements reveals the drawbacks of a conventional keeper used under a wide range of inter or intra-die variations.